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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78217A,78218A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78217A and 78218A are members of the 78K/II series of microcontrollers featuring a high-speed highperformance CPU. The PD78217A and 78218A are based on the PD78213 and 78214, and feature increased memory capacity and added functions, such as a timer/counter and macro servicing. Functions are described in detail in the following User's Manuals, which should be read when carrying out design work. PD78218A Subseries User's Manual: Hardware (IEU-1313) 78K/II Series User's Manual: Instruction (IEU-1311)
FEATURES
* Upper compatibility with PD78214 subseries (pin-compatible) * * * * High-speed instruction execution (at 12 MHz): 333 ns (PD78218A), 500 ns (PD78217A) On-chip high-performance interrupt controller On-chip A/D converter: 8 bits x 8 channels Number of I/O pins: 54 (PD78218A), 36 (PD78217A)
* Real-time output ports: 8 bits x 1 channel or 4 bits x 2 channels * Serial interface: 2 channels * Timer/counter: 16 bits x 1 channel and 8 bits x 3 channels
APPLICATION FIELDS
Printers, typewriters, OA equipment such as plain paper copiers (PPCs) and faxes, electronic music instruments, inverters, cameras, etc.
ORDERING INFORMATION
Part Number Package 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 x 14 mm) shrink DIP (750 mil) QFP (14 x 14 mm) On-Chip ROM None None 32K 32K On-Chip RAM 1024 1024 1024 1024
PD78217ACW PD78217AGC-AB8 PD78218ACW-xxx PD78218AGC-xxx-AB8
Remark
xxx is the ROM code suffix.
The information in this document is subject to change without notice. Document No. IC-2748E (O. D. No. IC-8131E) Date Published April 1995 P Printed in Japan The mark 5 shows revised points.
(c)
1991 1992
PD78217A, 78218A
78K/II Product Development
On-Chip A/D and D/A Converters Additional PWM Output Function Improved Macro Service and Timer/Counter Comparator Deletion
PD78234 Subseries
PD78244 Subseries
On-Chip D/A Converter Additional PWM Output Function Improved Macro Service and Timer/Counter Additional EEPROM Improved Macro Service and Timer/Counter
PD78224 Subseries
On-Chip A/D Converter Improved Timer/Counter and Baud Rate Generator Function Comparator Deletion
PD78214 Subseries
PD78218A Subseries
Expanded On-Chip Memory Capacity Improved Macro Service and Timer/Counter
PD78218A(A) PD78P218A PD78218A PD78217A
2
PD78217A, 78218A
FUNCTION LIST
Item Basic instructions (mnemonic) Minimum instruction execution time Instruction set 65
PD78217A
PD78218A
333 ns (at 12-MHz)
16-bit operation Multiply and divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulate BCD adjust, etc. ROM RAM None 1024 bytes Program memory: 64 Kbytes, data memory: 1 Mbytes 14 12 10 36 16 -- 8 ROM-less version 8 bits x 8 x 4 banks (memory mapping) 16-bit timer/counter Timer register x 1 Capture register x 1 Compare register x 2 Timer register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Capture register x 1 Compare register x 2 Timer register x 1 Compare register x 1 Pulse output capability Toggle output, PWM/PPG x 2 One-shot pulse output Pulse output capability (Real-time outputs, 4 bits x 2) EA pin = low level 28 54 34 16 32 Kbytes
On-chip memory capacity Address space I/O pins Input Output Input/Output Total
Note
Additional function pins
Pins with pull-up resistor LED direct drive outputs Transistor direct drive outputs
ROM-less mode setting General registers Timer/counter
8-bit timer/counter 1
8-bit timer/counter 2
Pulse output capability Toggle output PWM/PPG x 2
8-bit timer/counter 3
Real-time output port
Output port linked 8-bit timer/counter 1 4 bits x 2 channels UART : 1 channel (on-chip dedicated baud rate generator) CSI (3-wire serial I/O, SBI) : 1 channel 8-bit resolution x 8 channels 19 sources (external 7, internal 12) + BRK instruction 2-level priority order (programmable) 2 servicing modes (vectored interrupt, macro service) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 14 mm)
Serial interface A/D converter Interrupt
Package
Note Additional function pins are included in I/O pins. 3
PD78217A, 78218A
PIN CONFIGURATION (TOP VIEW)
64-pin plastic shrink DIP
P03 P04 P05 P06 P07 P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET X2 X1 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P02 P01 P00 P37/TO3 P36/TO2 P35/TO1 P34/TO0 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 AVREF AVSS VDD EA P33/SO/SB0 P32/SCK P31/TXD P30/RXD P27/SI P26/INTP5 P25/INTP4/ASCK P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI ASTB P40/AD0 P41/AD1
PD78217ACW PD78218ACW- x x x
m
P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 VSS
m
4
PD78217A, 78218A
64-pin plastic QFP
P67/REFRQ/AN7 P66/WAIT/AN6
64 P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET X2 X1 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P70/AN0
P37/TO3
P36/TO2
P35/TO1
P34/TO0
P65/WR
P07
P06
P05
P04
P03
P02
P01
P00
P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 AVREF AVSS VDD EA P33/SO/SB0 P32/SCK P31/TXD P30/RXD P27/SI P26/INTP5 P25/INTP4/ASCK
PD78217AGC-AB8 PD78218AGC- x x x -AB8
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33 32
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P41/AD1
P40/AD0
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
ASTB
VSS
5
PD78217A, 78218A
PIN IDENTIFICATION
P00 to P07 P20 to P27 P30 to P37 P40 P50 P60 P70 to to to to P47 P57 P67 P75 : Port 0 : Port 2 : Port 3 : : : : : : : : : : : : : : : : Port Port Port Port 4 5 6 7 RD WR WAIT ASTB REFRQ RESET X1, X2 EA AN0 to AN7 AVREF AVSS VDD VSS : Read Strobe : Write Strobe : : : : : : : : Wait Address Strobe Refresh Request Reset Crystal External Access Analog Input Reference Voltage
TO0 to TO3 CI RXD TXD SCK ASCK SB0 SI SO NMI INTP0 to INTP5 AD0 to AD7 A8 to A19
Timer Output Clock Input Receive Data Transmit Data Serial Clock Asynchronous Serial Clock Serial Bus Serial Input Serial Output Non-maskable Interrupt Interrupt From Peripherals Address/Data Bus
: Analog Ground : Power Supply : Ground
: Address Bus
6
PD78217A, 78218A
EXAMPLE OF SYSTEM CONFIGURATION (INVERTER AIR-CONDITIONER IN-DOOR UNIT)
Quick Heater AC 100 V Varistor Outdoor Unit
PD78218A
Remote Control Receive
INTP0 P55,P56 P32 2 Relay Driver
Wind Direction Setting
Wired Remote Control
AN0 P00-P03 AN1 AN2 P60-P63 AN3 4 Driver M 4 Driver M
Up-Down Wind Direction
Room Temperature Special Sensor Humidity Heat Exchanger Temperature
AN4 AN5 AN6 AN7
P04-P07
4
Driver
M
Right/ Left Wind Direction
P50-P54
5
Driver
M
Indoor Fan Motor
TXD Serial Communication Display Buzzer HA Control 2 8 P40-P47 P34 P35,P36 X1 X2 RXD RESET RESET
Stepping Motors
Right/ Left Wind Direction
7
PD78217A, 78218A
INTERNAL BLOCK DIAGRAM
ADDRESS BUS
A16-A19 (Expansion) A8-A15 AD0-AD7
PC NMI INTP0-INTP5 RXD TXD ASCK SCK SO/SB0 SI INTP3 TO0 TO1 PROGRAMMABLE INTERRUPT CONTROLLER
BUS CONTROL
UART BAUD RATE GENERATOR CLOCKED SERIAL INTERFACE TEMPORARY REGISTERS
SFR ADDRESS/DATA BUS
RD WR WAIT REFRQ ASTB
ALU ROM
TIMER/COUNTER (16 BITS) TIMER/COUNTER CHANNEL-1 (PS + 8 BITS) TIMER/COUNTER CHANNEL-2 (PS + 8 BITS) TIMER/COUNTER CHANNEL-3 (PS + 8 BITS)
SP PSW
DATA BUS (8)
INTP0 INTP1 INTP2 TO2 TO3
* MICRO ROM * MICRO- SEQUENCER
BOOLEAN PROCESSOR
SYSTEM CONTROL
* RAM (256 Bytes) * GR * MACRO SERVICE CHANNEL DATA BUS
X1 X2 RESET EA VDD VSS
BUS I/F
P00-P03 P04-P07 AN0-AN7 AVREF AVSS INTP5
REAL-TIME OUTPUT PORT (4 BITS x 2)
A/D CONVERTER
PORT
RAM
P0 P00 -P07
P2 P20 -P27
P3 P30 -P37
P4 P40 -P47
Note
P5 P50 -P57
Note
P6
P6
P7
Note
P60 P64 -P63 -P67
P70 -P75
Caution Note
Inernal ROM/RAM capacity varies depending on the product.
In case of the PD78217A, P40 to P47, P50 to P57, P64 and P65 cannot be used as ports.
8
PD78217A, 78218A
CONTENTS 1. 2. DIFFERENCES BETWEEN PD78218A AND PD78214 SUBSERIES ..................................................10 PIN FUNCTIONS ........................................................................................................................................11
2.1 2.2 2.3 PORTS .................................................................................................................................................................11 NON-PORT PINS ................................................................................................................................................12 PIN I/O CIRCUITS AND UNUSED PIN CONNECTION ...................................................................................13
3.
INTERNAL BLOCK FUNCTIONS ..............................................................................................................15
3.1 3.2 3.3 3.4 3.5 3.6 MEMORY SPACE ...............................................................................................................................................15 PORTS .................................................................................................................................................................17 REAL-TIME OUTPUT PORT ..............................................................................................................................19 TIMER/COUNTER UNIT ....................................................................................................................................20 A/D CONVERTER ...............................................................................................................................................22 SERIAL INTERFACE ...........................................................................................................................................24 3.6.1 Asynchronous Serial Interface ........................................................................................................ 25 3.6.2 Clock Synchronous Serial Interface ................................................................................................26
4.
INTERNAL/EXTERNAL CONTROL FUNCTION ......................................................................................27
4.1 INTERRUPTS ..................................................................................................................................................... 27 4.1.1 Interrupt Sources ..............................................................................................................................28 4.1.2 Vectored Interrupt .............................................................................................................................30 4.1.3 Macro Service ....................................................................................................................................30 4.1.4 Macro Service Application Examples .............................................................................................31 LOCAL BUS INTERFACE ...................................................................................................................................33 4.2.1 Memory Expansion ...........................................................................................................................33 4.2.2 Programmable Wait ..........................................................................................................................33 4.2.3 Pseudo-Static RAM Refresh Function ............................................................................................ 33 STANDBY ...........................................................................................................................................................34 RESET ..................................................................................................................................................................35
4.2
4.3 4.4
5. 6. 7. 8.
INSTRUCTION SET ...................................................................................................................................36 ELECTRICAL SPECIFICATIONS ................................................................................................................40 PACKAGE DRAWINGS .............................................................................................................................57 RECOMMENDED SOLDERING CONDITIONS ........................................................................................59
APPENDIX A. DEVELOPMENT TOOLS .........................................................................................................60 APPENDIX B. RELATED DOCUMENTS .........................................................................................................62
9
10
Series Name Part Number Minimum instruction execution time (at 12-MHz) PUSH PSW instruction execution time (number of clocks) Power voltage range On-chip memory ROM RAM I/O pins 16-bit timer/counter one-shot pulse output Macro service counter bit width Macro service type C MPD, MPT increments Macro service execution time Restrictions when data is transferred from macro service type A memory to SFR A/D converter Input voltage restrictions AVREF voltage restrictions Stabilization time for oscillation in STOP mode release Package 36
1. DIFFERENCES BETWEEN PD78218A AND PD78214 SUBSERIES
PD78218A Subseries PD78217A
500 ns
PD78214 Subseries PD78P218A PD78212
333 ns
PD78218A
333 ns
PD78213
500 ns
PD78214
PD78P214
333 ns
When stack area is an internal dual port RAM Other than above VDD=+5V10% ROM-less 32 Kbytes (mask ROM) 1024 bytes 54 Available 8/16 bits select capability (except type A) 16-bit increment
:6 :8
When stack area is an internal dual port RAM Other than above VDD=+5V10% 8 Kbytes (mask ROM) 384 bytes 54 36 Not available Only 8 bits Only low-order 8 bits increment (high-order 8 bits are unchanged) ROM-less 16 Kbytes (mask ROM) 512 bytes 54
: 5 or 7 : 7 or 9
VDD=+5V0.3V 32 Kbytes (PROM)
16 Kbytes (PROM)
Macro service depends on mode. Compare with user's manual of products. Generated when transfer source buffer (memory) address is 0FED0H to 0FEDFH. Generated when transfer data is in D0H to DFH.
Only pins involved in A/D conversion
Pins involved in A/D conversion and pins selected by ADM register bits ANI0 to ANI2 only: 0V to AVREF pin voltage 3.4 V to VDD
3.6 V to VDD
PD78217A, 78218A
Dedicated counter 15 bits or NMI active pulse width + dedicated counter 16 bits * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) * 64-pin ceramic shrink DIP (CERDIP, with window, 750 mil): PD78P218A only
NMI active pulse width + dedicated counter 16 bits
* * * * * *
64-pin plastic shrink DIP (750 mil) 64-pin plastic QUIP: Except PD78212 68-pin plastic QFJ: Except PD78212 64-pin plastic QFP (14 x 14 mm) 74-pin plastic QFP (20 x 20 mm) 64-pin ceramic shrink DIP (CERDIP, with window, 750 mil): PD78P214 only
PD78217A, 78218A
2. PIN FUNCTIONS
2.1 PORTS
Pin Name P00 to P07
I/O
Alternate Function Port 0 (P0):
Function
Output
Established as a real-time output port (4 bits x 2) Direct drive of transistors capability P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 to P37 P40 to P47
Note
Input
NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK INTP5 SI
Port 2 (P2): P20 cannot be used as a general-purpose port. (Non-maskable interrupt) However, the input level can be confirmed in the interrupt routine. The connection of the on-chip pull-up resistor can be specified as a 6-bit unit for P22 to P27 by software.
Input/ output
RxD TxD SCK SO/SB0 TO0 to TO3
Port 3 (P3): The input/output specifiable bit-wise. Input mode pins specifiable for on-chip pull-up resistor connection as a batch by software.
Input/ output
AD0 to AD7
Port 4 (P4): The input/output specifiable as an 8-bit batch. The connection of the on-chip pull-up resistor specifiable as an 8-bit batch by software. LED direct drive capability.
P50 to P57
Note
Input/ output
A8 to A15
Port 5 (P5): The input/output specifiable bit-wise. Input mode pins specifiable for on-chip pull-up resistor connection as a batch by software. LED direct drive capability.
P60 to P63 P64 P65 P66 P67 P70 to P75
Note Note
Output Input/ output
A16 to A19 RD WR WAIT/AN6 REFRQ/AN7
Port 6 (P6): P64 to P67 enables to specify the input/output bit-wise. The connection of the on-chip pull-up resistor to input mode pins can be specified as a batch for P64 to P67 by software.
Input
AN0 to AN5
Port 7 (P7)
Note
In case of the PD78217A, these cannot be used as ports.
11
PD78217A, 78218A
2.2
NON-PORT PINS
Alternate Function P34 to P37 P23 /INTP2 P30 P31 P25/INTP4 P33/SO P27 P33/SB0 P32 P20 P21 P22 P23/CI P24 P25/ASCK P26 Input/output P40 to P47 Output Output Output Output Input Output Output Input Input P67/AN7 P50 to P57
Note Note
Pin Name TO0 to TO3 CI RXD TXD ASCK SB0 SI SO SCK NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT ASTB REFRQ RESET X1 X2 EA
I/O Output Input Input Output Input Input/output Input Output Input/output Input
Function Timer output Count clock input to 8-bit timer/counter 2 Serial data input (UART) Serial data output (UART) Baud rate clock input (UART) Serial data input/output (SBI) Serial data input (3-wire serial I/O) Serial data output (3-wire serial I/O) Serial clock input/output (SBI, 3-wire serial I/O) External interrupt request
Time multiplexing address/data bus (external memory connection) Upper address bus (external memory connection) Upper address when extending address (external memory connection) Read strobe into external memory Write strobe into external memory Wait insertion Address (A0 to A7) latch timing output (during external memory access) Refresh pulse output into external pseudo-static memory Chip reset Crystal connection for system clock oscillation (external clock input to X1 enabled)
P60 to P63 P64 P65
Note Note
P66/AN6
Input
ROM-less operating specification (external access of the same space as internal ROM). Used high for the PD78218A and used low for the PD78217A.
AN0 to AN5 AN6, AN7 AVREF AVSS VDD VSS
Input
P70 to P75
P66/WAIT, P67/REFRQ
Analog voltage input for A/D converter
Reference voltage apply for A/D converter GND for A/D converter Positive power supply GND
Note
In case of the PD78217A, these cannot be used as ports.
12
PD78217A, 78218A
2.3 PIN I/O CIRCUITS AND UNUSED PIN CONNECTION The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Fig. 2-1. Table 2-1 Input/Output Circuit Type of Each Pin
Pin Name P00 to P07 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK P26/INTP5 P27/SI P30/RXD P31/TXD P32/SCK P33/SB0/SO P34/TO0 to P37/TO3 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/AN6 P67/REFRQ/AN7 P70/AN0 to P75/AN5 ASTB RESET EA AVREF AVSS
Input/Output Circuit Type 4 2
I/O Output Input Leave open.
Unused Pin Connection
Connected to VDD or VSS .
2-A
Connected to VDD .
5-A
Input/output
Input Output
: Connected to VDD. : Leave open.
8-A 10-A 5-A
4 5-A
Output Input/output
Leave open. Input Output : Connected to VDD. : Leave open. : Connected to VDD. : Leave open.
Note
11
Input Output
9 4 2 1
Input Output Input
Connected to VSS . Leave open.
Connected to VSS or VDD . Connected to VSS .
Note
Note
A voltage outside the range AVSS to AVREF should not be applied, as this may damage the PD78217A/78218A. If the input/output mode is undefined for the input/output dual-function pins, connect these pins to VDD via a resistor of several ten k. (Especially if the reset input pin exceeds the low-level input voltage at power-on or in case of input/ output switching by software.)
Caution
Remark
The type numbers are standardized for 78K series, therefore they are not always consecutive numbers for each product (some circuits are not incorporated).
13
PD78217A, 78218A
Fig. 2-1 Pin Input/Output Circuits
Type 1 VDD Type 2-A VDD
P
P
IN N
pullup enable
IN
Schmitt-Triggered Input with Hysteresis Characteristic Type 2 IN Schmitt-Triggered Input with Hysteresis Characteristic Type 4 data VDD P OUT output disable N input enable data output disable Type 5-A pullup enable VDD P IN / OUT N VDD P
Push-pull output which enables output to be high-impedance (both P-ch and N-ch off). Type 8-A pullup enable VDD data P IN / OUT output disable N
VDD P
Type 9
IN
P N
Comparator + Vref (Threshold Voltage)
input enable
Type 10-A
VDD
Type 11
VDD P VDD
pullup enable VDD data open drain output disable P
P
pullup enable data P
IN / OUT IN / OUT output disable Comparator + N
N
P N
Vref (Threshold Voltage) input enable
14
PD78217A, 78218A
3. INTERNAL BLOCK FUNCTIONS
3.1 MEMORY SPACE A memory space of 1 Mbytes can be accessed. Fig. 3-1 shows that memory space. The program memory mapping differs depending on the EA pin status. (1) PD78217A (EA = L) The program memory is mapped onto external memory (64256 bytes: 00000H to 0FAFFH). This area can also be used as data memory. The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory. (2) PD78218A (EA = H) The program memory is mapped onto internal ROM (32 Kbytes: 00000H to 07FFFH) and external memory (31488 bytes: 08000H to 0FAFFH). The external memory is accessed in the external memory expansion mode. The area mapped onto the external memory can also be used as data memory. The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory.
15
PD78217A, 78218A
Fig. 3-1 Memory Map
EA = L (ROM-Less Mode) Note3
EA = H FFFFFH
Extended Address
Data Memory
External Memory Note1 (960 Kbytes)
Note1
10000H
0FFFFH 0FFDFH 0FFD0H 0FF00H
0FEFFH Special Function Register (SFR)
Note2
General Register (32 bytes) Macro Service Control Word (30 bytes) Data Area (1024 bytes)
(256 bytes)
0FEE0H 0FEDFH
0FEC2H
Memory Space (1 Mbytes)
0FEFFH
Data Memory
Internal RAM (1024 bytes) 0FB00H 0FB00H 07FFFH
Normal Address (64 Kbytes)
0FAFFH
Program Memory/ Data Memory
01000H 00FFFH CALLF Entry Area (2 Kbytes) 08000H 07FFFH 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H Program Area (1920 bytes) CALLT Table Area (64 bytes) Vector Table Area (64 bytes) 00FFFH
Program Memory/ Data Memory
Internal ROM (32 Kbytes)
00000H
Notes 1. Accessed by 1-Mbyte expansion mode. Shaded areas denote internal memory. 2. Accessed by external memory expansion mode. 3. The PD78217A applies only when EA = L.
16
Program Memory / Data Memory
External Memory Note2 (31488 bytes)
Program Area (28 Kbytes)
External Memory (64256 bytes)
PD78217A, 78218A
3.2
PORTS
The PD78217A/78218A has the ports shown in Fig. 3-2 which allow various kinds of control. The functions of each port are shown in Table 3-1. For ports 2 to 6, on-chip pull-up resistor can be specified by software at input. Fig. 3-2 Port Configuration
P00-P07
8
Port 0
P20-P27
8
Port 2
P30 Port 3 P37
P40-P47
8
Port 4
Note
P50 Port 5 P57
Note
P60-63
4 Port 6
Note
P64 P67
P70-P75
6
Port 7
Note
In case of the PD78217A, P40 to P47, P50 to P57, P64, and P65 cannot be used as ports.
17
PD78217A, 78218A
Table 3-1 Port Function
Name Port 0
Pin Name P00 to P07
Function Output or high-impedance specifiable as an 8-bit batch. Can also operate as 4 bits real-time output (P00 to P03, P04 to P07). Transistor direct drive capability.
Designation of Software Pull-Up -----
Port 2 Port 3
P20 to P27 P30 to P37
Input port Input or output specifiable bit-wise.
6-bit batch (P22 to P27) Input mode pins specifiable as a batch
Port 4
Note
P40 to P47
Input or output specifiable as an 8-bit batch. LED direct drive capability.
8-bit batch
Port 5
Note
P50 to P57
Input or output specifiable bit-wise. LED direct drive capability.
Input mode pins specifiable as a batch ----- Input mode pins specifiable as a batch
Port 6
Note
P60 to P63 P64 to P67
Output port Input or output specifiable bit-wise.
Port 7
P70 to P75
Input port
-----
Note
In case of the PD78217A, P40 to P47, P50 to P57, P64, and P65 cannot be used as ports.
18
PD78217A, 78218A
3.3
REAL-TIME OUTPUT PORT
The real-time output port outputs the data stored in the buffer in synchronization with timer match interrupts or external interrupts. A jitterless pulse output is obtained by means of this. Therefore, it is most suitable for applications which output any pattern at any interval time. (Stepping motor open loop control, etc.) Port 0 and the buffer register are the core elements of the configuration, as shown in Fig. 3-3. Fig. 3-3 Real-Time Output Port Block Diagram
Internal Bus
8
4
4
Real-Time Output Port Control Register
Buffer Register
P0H
P0L
8
INTP0 (From Outside) INTC10 (From Timer) INTC11 (From Timer) Output Trigger Control Circuit
4
4
Output Latch (P0)
P07
P00
19
PD78217A, 78218A
3.4
TIMER/COUNTER UNIT
The PD78217A/78218A has a 16-bit timer/counter unit for 1 channel and 8-bit timer/counter units for 3 channels. Table 3-2 Type and Function of Timer/Counter
Unit Type & Function Interval timer Type External event counter One-shot timer Timer output Toggle output PWM/PPG output Function One-shot pulse output Real-time output Pulse amplitude measurement Number of interrupt requests Clock source of serial interface
16-Bit Timer/ Counter 2 chs
8-Bit Timer/ Counter 1 2 chs
8-Bit Timer/ Counter 2 2 chs
8-Bit Timer/ Counter 3 1 ch
--- ---
2 chs
--- ---
--- --- --- --- --- --- 2 chs
--- ---
--- --- --- --- --- ---
---
2 ---
2 ---
2 ---
1
Since 7 interrupt requests are supported in total, it can also function as timer for 7 channels. Remark The one-shot pulse output function activates the pulse output level by software, and inactivates it by hardware (interrupt request signal). This function is different from the one-shot timer function of 8-bit timer/counter 2.
20
PD78217A, 78218A
Fig. 3-4 Timer/Counter Unit Block Diagram 16-bit timer/counter unit
Software Trigger fCLK/8 Timer Register TM0 OVF
Compare Register CR00
Pulse Output Control
Match
TO0
Compare Register CR01
Match
TO1
INTP3
Edge Detection
INTC00 Capture Register CR02 INTP3 INTC01
8-bit timer/counter unit 1
fCLK/16 Prescaler Timer Register TM1 OVF
Compare Register CR10
Match
INTC10 To Real-Time Output Port
INTP0
Edge Detection
Capture/Compare Register CR11
Match
INTC11
INTP0
8-bit timer/counter unit 2
fCLK/16 Prescaler
Timer Register TM2
OVF
Pulse Output Control
INTP2/CI
Edge Detection
Event Input INTP2
Compare Register CR20
Match
TO2
Compare Register CR21
Match
TO3
INTP1
Edge Detection
Capture Register CR22
INTC20 INTC21
INTP1
8-bit timer/counter unit 3
fCLK/8 Prescaler Timer Register TM3 Clear UART
Compare Register CR30
CSI Match INTP4/ INTC30
INTP4/ ASCK
Edge Detection
OVF: Overflow Flag
21
PD78217A, 78218A
3.5
A/D CONVERTER
The PD78217A/78218A incorporate the analog/digital (A/D) converter with 8-channel multiplexed analog input (AN0 to AN7). The conversion method used is successive approximation. After the A/D conversion results are generated, they are held in the 8-bit A/D conversion result register (ADCR), which may allow high-speed and high-precision conversion (conversion time: Approx. 30 s; at 12-MHz operation). The following two modes are available for starting A/D conversion: * * Hardware start : Starts conversion by trigger input (INTP5) Software start : Starts conversion by the A/D converter mode register (ADM) bit setting
The following two modes of operation after starting are available: * * Scan mode : Multiple analog input are selected sequentially and conversion data is obtained from all pins.
Select mode : The analog input is fixed at one pin and a continuous conversion value is obtained.
The above modes and the conversion operation are all stopped by ADM. If the conversion result is transferred to the ADCR, an interrupt request INTAD is generated, (except in software start select mode). Therefore, the conversion value can be transferred to memory continuously using macro service (See section 4.1.3 "Macro Service"). Table 3-3 INTAD Generation Mode
Scan Mode Hardware start Software start
Select Mode
---
22
PD78217A, 78218A
Fig. 3-5 A/D Converter Block Diagram
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive Approximation Register (SAR) Edge Detector Conversion Trigger Controller
Series Resistor String
Input Selector
Sample & Hold Circuit R/2 R
AV REF
INTP5
INTAD
Tap Selector
R/2 AV SS Selector Interrupt Request
Voltage Comparator
INTP5 Trigger Enable
8 A/D Conversion Result Register (ADCR)
A/D Converter Mode Register (ADM)
8
8
Internal Bus
23
PD78217A, 78218A
3.6
SERIAL INTERFACE
The PD78217A/78218A has two independent serial interfaces. * * Asynchronous serial interface (UART) Clock synchronous serial interface (CSI) * 3-wire serial I/O * Serial bus interface (SBI) Therefore, communication with external devices and local communication inside the system can be performed simultaneously (See Fig. 3-6). Fig. 3-6 Serial Interface Example
(a) UART + SBI
PD78218A (Master)
PD4711A
[UART] RS-232-C Driver [SBI] RXD TXD Port SB0 SCK
VDD
PD75402A (Slave)
SB0 SCK
PD75328 (Slave)
SB0 SCK LCD
(b) UART + 3-wire serial I/O
PD78218A (Master)
PD4711A
[UART] RS-232-C Driver RXD TXD Port [3-Wire Serial I/O] SO SI SCK
Note
PD78C11A (Slave)
SI SO SCK Port INT
INTPm Port
PD78C14 (Slave)
SI SO SCK INTPn Port
Note
Port INT
Note Handshake Line
24
PD78217A, 78218A
3.6.1
Asynchronous Serial Interface
The PD78217A/78218A incorporates UART (Universal Asynchronous Receiver Transmitter) as the asynchronous serial interface. UART is used to send/receive one byte of data following a start bit. The UART incorporates a dedicated baud rate generator which can generate a wide range of desired baud rates and also determine baud rates by scaling the ASCK pin input clocks or 8-bit timer/counter 3 output (TM3 output), allowing transmission/reception with a variety of baud rates. If the UART dedicated baud rate generator is used, the MIDI standard baud rate (31.25 kbps) can also be obtained. Fig. 3-7 Asynchronous Serial Interface (UART) Block Diagram
Internal Bus
Receive Buffer
RXB
RXD
Receive Shift Register
Transmit Shift Register
TXS
TXD
Receive Control Parity Check
INTSR INTSER
Transmit Control Parity Addition
INTST
1/16
1/16
UART Dedicated Baud Rate Generator fCLK 1/N1
Selector
1/N2
ASCK
Selector
TM3 Output
1/2
fCLK: Internal system clock frequency (System Clock Frequency/2)
Selector
25
PD78217A, 78218A
3.6.2
Clock Synchronous Serial Interface
The master device starts transmission by activating the serial clock and transfers one-byte data in synchronization with this clock. Fig. 3-8 Clock Synchronous Serial Interface Block Diagram
Internal Bus
Set Clear Selector SI SIO Shift Register Output Latch
SO/SB0
N-ch Open-drain output also possible (SB0: SBI) Bus Release Command/ Acknowledge Detector
Busy/ Acknowledge Generator
SCK
Serial Clock Counter
Interrupt Generator
INTCSI
TM3 Output/2 Selector Serial Clock Controller fCLK/8 fCLK/32
fCLK: Internal System Clock Frequency (System Clock Frequency/2) (1) 3-wire serial I/O This is an interface for communicating with devices incorporating a conventional clock synchronous serial interface. Basically, communication is performed with three lines, one serial clock line (SCK) and two serial data lines (SI, SO). When connecting to multiple devices, a handshake line is necessary. (2) SBI Communication with multiple devices is performed with one serial clock line (SCK) and one serial bus line (SB0). This is NEC's standard serial interface. The master device selects the slave device to be communicated with by outputting its "address" from the SB0 pin. Therefore, "commands" and "data" perform transfer and receive between the master and slave.
26
PD78217A, 78218A
4. INTERNAL/EXTERNAL CONTROL FUNCTION
4.1 INTERRUPTS Two interrupt request servicing methods can be selected, as shown in the following table. Table 4-1 Interrupt Request Servicing
Service Mode Vectored interrupt
Servicing Subject Software
Service Branches to service routine, and executes (any process contents) Data transfer, etc., between memory and I/O (fixed process contents)
PC, PSW Contents With save and return
Macro service
Firmware
Hold
27
PD78217A, 78218A
4.1.1
Interrupt Sources
There are 19 types of interrupt sources and a BRK instruction execution, as shown in Table 4-2. The priority of the interrupt servicing can be set to 2 levels (high and low priority levels). Therefore, the levels of nest control when the interrupt is in progress and when interrupt requests occur simultaneously (see Fig. 4-1, Fig. 4-2) can be separated. Nesting will always take place in the macro service (It won't be put on hold). The default priority is the priority level (fixed) to service the interrupt requests which occur at the same level simultaneously (see Fig. 4-2). Table 4-2 Interrupt Sources
Type Software Nonmaskable Maskable
Default Priority
Source Name BRK NMI Instruction execution Pin input edge detection Trigger
Internal/ External ----- External
Macro Service ---
0 (highest) 1 2 3 4 5 6 7 8 9
INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC21 INTP4 INTC30
Pin input edge detection (TM1 capture trigger) Pin input edge detection (TM2 capture trigger) Pin input edge detection (TM2 event counter input) Pin input edge detection (TM0 capture trigger) TM0 to CR00 match signal generation TM0 to CR01 match signal generation TM1 to CR10 match signal generation TM1 to CR11 match signal generation TM2 to CR21 match signal generation Pin input edge detection TM3 to CR30 match signal generation Pin input edge detection A/D converter conversion termination (transfer to ADCR) TM2 to CR20 match signal generation ASI receive error generation ASI receive termination ASI transmit termination CSI transfer termination --- External Internal External Internal Internal
10
INTP5 INTAD
11 12 13 14 15 (lowest)
INTC20 INTSER INTSR INTST INTCSI
TM0 : 16-bit timer TM1 to TM3 : 8-bit timer ASI : Asynchronous serial interface CSI : Clock synchronous serial interface
28
PD78217A, 78218A
Fig. 4-1 Servicing Example when an Interrupt Request Occurrence is Issued while an Interrupt is Serviced
Main Routine [Nesting 1] Servicing of a Servicing of b Macro Service Request b Vectored Interrupt Request a (Low-Priority Level) Servicing of c Vectored Interrupt Request c (High-Priority Level) Servicing of d Macro Service Request d [Nesting 2] [Nesting 3]
Servicing of e Servicing of f Macro Service Request f Vectored Interrupt Request e (High-Priority Level) Macro Service Request h
Vectored Interrupt Request g (Low-Priority Servicing Level: Pending) Servicing of h of g
Fig. 4-2 Servicing Example of Simultaneous Interrupt Requests
Main Routine [Nesting 1] Servicing of b [Nesting 2]
* Vectored Interrupt Request a (Low-Priority Level) * Macro Service Request b (High-Priority Level) * Macro Service Request c (Low-Priority Level) * Vectored Interrupt Request d (High-Priority Level) Default Priority: a > b > c > d
Servicing of d
Servicing of c
Servicing of a
29
PD78217A, 78218A
4.1.2 Vectored Interrupt The memory contents of the vector table address, which corresponds to the interrupt source, is branched into the service routine as a destination address. As the CPU executes the interrupt servicing, the following operations occur. * * When branch : When return : Saving the CPU status (PC, PSW contents) to the stack. Returning the CPU status (PC, PSW contents) from the stack.
The RETI instruction executes returning to the main routine from the service routine. Table 4-3 Vector Table Address
Interrupt Source BRK NMI INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11
Vector Table Address 003EH 0002H 0006H 0008H 000AH 000CH 0014H 0016H 0018H 001AH
Interrupt Source INTC21 INTP4 INTC30 INTP5 INTAD INTC20 INTSER INTSR INTST INTCSI
Vector Table Address 001CH 000EH
0010H
0012H 0020H 0022H 0024H 0026H
4.1.3 Macro Service This is a function to transfer data between the memory and special function registers (SFR) without going through the CPU. The macro service controller accesses the memory and SFR, and transfers data directly without fetching it. High-speed data transfer is enabled because no data is saved, restored or fetched. Fig. 4-3 Macro Service
Read CPU Memory Write
Macro Service Controller
Write SFR Read
Internal Bus
30
PD78217A, 78218A
4.1.4
Macro Service Application Examples
(1) Transmit operation of serial interface
Transmit Data Storage Buffer (Memory) Data n Data n-1
Data 2 Data 1
Internal Bus
TXD
Transmit Shift Register TXS (SFR)
Transmission Control
INTST
Whenever the macro service request INTST is generated, the next transmit data is transferred to TXS from the memory. When the data n (last byte) is transferred to TXS (the transmit data storage buffer becomes empty), a vectored interrupt request INTST is generated. (2) Receive operation of serial interface
Receive Data Storage Buffer (Memory) Data n Data n-1
Data 2 Data 1
Internal Bus
Receive Buffer
RXB (SFR)
RXD
Receive Shift Register
Receive Control
INTSR
Whenever the macro service request INTSR is generated, the receive data is transferred to the memory from RXB. When the data n (last byte) is transferred to the memory (the receive data storage buffer becomes empty), the vectored interrupt request INTSR is generated.
31
PD78217A, 78218A
(3) Real-time output port The INTC10 and INTC11 become output triggers of the real-time output port. In the macro service for them, the next output pattern and interval can be set simultaneously. Therefore, the INTC10 and INTC11 can control 2 system stepping motor independently. Also, they can be applied to control a PWM or DC motor, etc.
Output Pattern Profile (Memory) Pn Pn-1
Output Timing Profile (Memory) Tn Tn-1
P2 P1
T2 T1
Internal Bus
Internal Bus
(SFR)
P0L
Match
CR10
(SFR)
INTC10 Output Latch P00-P03 TM1
Whenever the macro service request INTC10 is generated, the pattern and timing are transferred to P0L and CR10, respectively. When the contents of the TM1 match with the contents of the CR10, the next INTC10 is generated and the contents of the P0L are sent to the output latch. If Tn (last byte) is sent to CR10, a vectored interrupt request INTC10 is generated. The same operation is available for INTC11 (differences: CR10 CR11, P0L P0H, P00-P03 P04-P07).
32
PD78217A, 78218A
4.2
LOCAL BUS INTERFACE
The PD78217A/78218A can be connected to an external memory and I/O (memory mapped I/O), and supports the 1M-byte memory space (see Fig.3-1). Fig. 4-4 Local Bus Interface Example
PD78218A
A16-A19 Decoder
RD WR REFRQ Pseudo SRAM PROM PD27C256A
Kanji-Character Generator PD24C1000
AD0-AD7
Data Bus
ASTB
Latch
A8-A15
Address Bus
Gate Array I/O Expansion Centronics I/F, etc.
4.2.1
Memory Expansion
The following modes have been prepared as a memory expansion function. * External memory expansion mode : Expands the program memory and data memory to 31488 bytes (64256 bytes for the PD78217A) externally. However, this area can be used unconditionally under the ROM-less mode (EA = L). * 1-Mbyte expansion mode : Expands the data memory by 960 Kbytes and become a 1-Mbyte memory space.
4.2.2
Programmable Wait
A wait can be independently inserted to the memory mapped on both a normal address (00000H to 0FFFFH) and an expanded address (10000H to FFFFFH). Therefore, the efficiency of the entire system is not decreased. 4.2.3 Pseudo-Static RAM Refresh Function
The refresh operations are as follows. * Pulse refresh : Outputs the refresh pulse to REFRQ pin in synchronization with a bus cycle. * Power-down self refresh : Outputs a low-level to the REFRQ pin in the standby mode and holds the contents of the pseudo-static RAM.
33
PD78217A, 78218A
4.3
STANDBY
This is a function to reduce the power consumption of the chip. The following modes are available. * HALT mode : Stops the operation clock of the CPU. The average power consumption is reduced by switching from normal mode to HALT mode and vice-versa. * STOP mode : Stops the oscillator. This stops all operation in the chip and enables minute power consumption consisting only of leakage current. These modes are programmable. The macro service is started from the HALT mode. Fig. 4-5 Standby Status Flow
Program Operation
OP R t Se TI np
Ma 1-B
E ES
HALT Set
STOP (Standby)
I NM
Inp
ut
RESET Input NMI Input Vectored Interrupt Request Note 2
ST
ut
Se rvi y ce Da te T Re qu Te ta T rans es rm ra fer t ina nsf tio er n
No te 4
cro
Ma
Interrupt Request at Interrupt Disable
HALT (Standby)
fer ns Tra fer ote 3 yte ns N 1-B a Traation t Da rmin Te cro
S
ic erv
eR
eq
s ue
t
Macro Service
Vectored Interrupt Request
Note 1
Notes 1. In case a vectored interrupt request is a low-priority level (status to disable interrupt of a low-priority sequence under the HALT setting). 2. In case a vectored interrupt request is a high-priority level or in case of the status to enable interrupt of a low-priority sequence under the HALT setting. 3. In case a macro service is a high-priority level (status to disable interrupt of a low-priority sequence under the HALT setting). 4. In case a macro service is a high-priority level or in case of the status to enable interrupt of a low-priority sequence under the HALT setting.
34
PD78217A, 78218A
4.4
RESET
When a low level is input to the RESET pin, the internal hardware is initialized (reset state). When the RESET input changes from low level to high level, the following data is set in the program counter (PC). * Lower 8 bits of PC : * Upper 8 bits of PC : Contents of 0000H address Contents of 0001H address
The contents of the PC set the destination address and the program starts to be executed from the address. Therefore, it can start from any address by reset start. Please set the program for the contents of each register as required. A noise eliminator has been incorporated in the RESET input circuit to prevent any error from noise. This noise eliminator is a sampling circuit based on analog delay. Fig. 4-6 Reset Acknowledge
Delay
Delay
Delay
PC Initialization
Instruction Execution of Reset Start Address
RESET (Input)
Internal Reset Signal
Reset Start
Reset End
Set the RESET signal active in the reset operation at power-on until the oscillation stabilization time (approx. 40 ms) elapses. Fig. 4-7 Reset Operation at Power-On
Oscillation Stabilization Time
Delay
PC Initialization
Instruction Execution of Reset Start Address
VDD
RESET (Input)
Internal Reset Signal
Reset End
35
PD78217A, 78218A
5. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP Table 5-1 Instructions Classified by 8-Bit Addressing Mode
2nd Operand #byte 1st Operand
Note1
r A r' MOV XCH
saddr sfr saddr' MOV MOV MOV MOV XCH XCH XCH XCH Note1 Note1 Note1 Note1 ADD ADD ADD ADD mem &mem !addr16 &!addr16 PSW n
None
Note2
A
ADD
MOV
MOV
MOV ROL ROLC ROR RORC SHR SHL
r
MOV
MOV XCH Note1 ADD
MULU DIVUW INC DEC DBNZ
r1 saddr MOV Note1 ADD MOV Note1 ADD MOV MOV XCH Note1 ADD
INC DBNZ DEC PUSH POP
sfr mem & mem mem1 &mem1 !addr16 &!addr16 PSW STBC
MOV MOV
ROR4 ROL4 MOV MOV MOV MOV MOV PUSH POP
Notes
1. 2.
ADDC, SUB, SUBC, AND, OR, XOR and CMP are the same as ADD. There is no 2nd operand, or the 2nd operand is not an operand address.
36
PD78217A, 78218A
(2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, SHLW, PUSH, POP Table 5-2 Instructions Classified by 16-Bit Addressing Mode
2nd Operand #word 1st Operand ADDW SUBW CMPW AX
rp saddrp rp' ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW sfrp mem1 &mem1 SP n None
AX
MOVW
MOVW
MOVW
rp
MOVW
MOVW
SHLW SHRW
INCW DECW PUSH POP
saddrp sfrp mem1 &mem1 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
INCW DECW
37
PD78217A, 78218A
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Table 5-3 Instructions Classified by Bit Manipulation Instruction Addressing Mode
2nd Operand CY 1st Operand MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 A.bit /A.bit X.bit /X.bit
saddr. bit MOV1 AND1 OR1 XOR1
/saddr. sfr.bit bit MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 /sfr.bit PSW.bit
/PSW. bit
None
Note
CY
AND1 OR1
AND1 OR1
AND1 OR1
SET1 CLR1 NOT1 SET1 CLR1 NOT1 BT BF BTCLR SET1 CLR1 NOT1 BT BF BTCLR SET1 CLR1 NOT1 BT BF BTCLR SET1 CLR1 NOT1 BT BF BTCLR SET1 CLR1 NOT1 BT BF BTCLR
A.bit
MOV1
X.bit
MOV1
saddr.bit
MOV1
sfr.bit
MOV1
PSW.bit
MOV1
Note There is no 2nd operand, or the 2nd operand is not an operand address.
38
PD78217A, 78218A
(4) Call/branch instructions CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, BNE Table 5-4 Instructions Classified by Call/Branch Instruction Addressing Mode
Operands of Instruction Address Basic instructions Compound instructions
$addr16 BR BCNote BT BF BTCLR DBNZ
!addr16 CALL BR
rp CALL BR
!addr11 CALLF
[addr5] CALLT
Note
BL, BNC, BNL, BZ, BE, BNZ and BNE are the same as BC.
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, NOP, EI, DI, SEL
39
PD78217A, 78218A
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
PARAMETER
SYMBOL VDD
TEST CONDITIONS
RATING -0.5 to +7.0 -0.5 to VDD +0.5 -0.5 to +0.5 -0.5 to VDD +0.5
UNIT V V V V V V mA mA mA mA C C
Supply voltage
AVREF AVSS
Input voltage Output voltage Output current, low
VI1 VI2 VO Per pin IOL All output pins Per pin Note
-0.5 to AVREF +0.5 -0.5 to VDD +0.5 15 100 -10 -50 -40 to +85 -65 to +150
Output current, high
IOH All output pins TA Tstg
5
Operating ambient temperature Storage temperature
Note
P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins. However, VI1 absolute maximum ratings should also be satisfied.
Caution
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
OPERATING CONDITIONS
5
CLOCK FREQUENCY 4 MHz fXX 12 MHz
OPERATING AMBIENT TEMPERATURE (TA) -40 to +85 C
SUPPLY VOLTAGE (VDD) +5 V 10 %
CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance
SYMBOL CI CO CIO
TEST CONDITIONS f = 1 MHz unmeasured pins returned to 0 V.
MIN.
TYP.
MAX. 20 20 20
UNIT pF pF pF
40
PD78217A, 78218A
OSCILLATOR CHARACTERISTICS (TA= -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
RESONATOR RECOMMENDED CIRCUIT
PARAMETER
MIN.
MAX.
UNIT
Ceramic resonator or crystal resonator
VSS X1
X2 Oscillator frequency (fXX) 4 12 MHz
C1
C2
X1 External clock HCMOS Inverter
X2
X1 input frequency (fX)
4
12
MHz
X1 input rising/falling time (tXR , tXF) X1 input high/low level width (tWXH , tWXL)
0
30
ns
30
130
ns
Caution
When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. Do not ground it to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
41
PD78217A, 78218A
RECOMMENDED OSCILLATOR CONSTANTS CERAMIC RESONATOR
MANUFACTURER
FREQUENCY [MHz] 12
PART NUMBER
RECOMMENDED CONSTANTS C1 [pF] C2 [pF] 30
CSA12.0MTZ Murata Mfg. CST12.0MTW EFOGC1205C4 Matsushita Electronics Parts 12
Note
30
Capacitor on-chip type Capacitor on-chip type 33 33 33 33
EFOEC1205C4 EFOEN1205C4 FCR12.0M2S
5 5
TDK Co. 12
FCR12.0MC
Capacitor on-chip type
Note
Production discontinued.
42
PD78217A, 78218A
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
PARAMETER Input voltage, low
SYMBOL VIL VIH1
TEST CONDITIONS
MIN. 0
TYP.
MAX. 0.8 VDD AVREF VDD 0.45
UNIT V V V V V V V V V
Pins except for Note 1 and Note 2 Pin of Note 1 Pin of Note 2 IOL = 2.0 mA IOL = 8.0 mA
Note3
2.2 2.2 0.8 VDD
Input voltage, high
VIH2 VIH3 VOL1
Output voltage, low VOL2 VOH1 Output voltage, high VOH2 VOH3 X1 input current, low X1 input current, high Input leakage current Output leakage current AVREF current IIL IIH ILI ILO AIREF IDD1 VDD supply current IDD2 Data retention voltage VDDDR HALT mode fXX = 12 MHz STOP mode STOP mode Pull-up resistor RL VI = 0 V VDDDR = 2.5 V VDDDR = 5 V 10 % 15 2.5 2 5 40 7 20 5.5 20 50 80 mA V 1.0 VDD-1.0 VDD-0.5
Note4
IOH = -1.0 mA IOH = -100 A IOH = -5.0 mA 0 V VI VIL VIH3 VI VDD 0 V VI VDD 0 V VO VDD Operating mode fXX = 12 MHz Operating mode fXX = 12 MHz
2.0 -100 100 10 10 1.5 20 5.0 40
A A A A
mA mA
A A
k
Data retention current
IDDDR
Notes 1. P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins. 2. X1, X2, RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/ INTP5, P27/SI, P32/SCK, P33/SO/SB0, EA pins 3. P40/AD0 to P47/AD7, P50/A8 to P57/A15 pins 4. P00 to P07 pins
43
PD78217A, 78218A
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V) READ/WRITE OPERATION (1/2)
PARAMETER X1 input clock cycle time Address setup time (to ASTB) Address hold time (from ASTB)
Note
SYMBOL tCYX tSAST * tHSTA tHRA tHWA tDAR * tFAR * tDAID * tDSTID * tDRID * tDSTR * tHRID tDRA * tDRST * tWRL * tWSTH * tDAW * tDSTOD * tDWOD tDSTW1 *
TEST CONDITIONS
MIN. 82 52 25 30 30 129 11
MAX. 250
UNIT ns ns ns ns ns ns ns
Address hold time (from RD) Address hold time (from WR) RD delay time from address Address float time (from RD) Data input time from address Data input time from ASTB Data input time from RD RD delay time from ASTB Data hold time (from RD) Address active time from RD ASTB delay time from RD RD low-level width ASTB high-level width WR delay time from address Data output time from ASTB Data output time from WR WR delay time from ASTB
No. of waits = 0 No. of waits = 0 No. of waits = 0 52 0 124 124 No. of waits = 0 124 52 129
228 181 100
ns ns ns ns ns ns ns ns ns ns
142 60 Refreshing disabled Refreshing enabled No. of waits = 0 Refreshing enabled 52 129 146 22 20 42 Refreshing disabled No. of waits = 0 Refreshing enabled No. of waits = 0 196
ns ns ns ns ns ns ns ns ns
tDSTW2 * Data setup time (to WR) Data setup time (to WR) Data hold time (from WR)
Note
tSODWR * tSODWF * tHWOD tDWST * tWWL1 *
ASTB delay time from WR
WR low-level width tWWL2 * WAIT input time from address WAIT input time from ASTB tDAWT * tDSTWT * 114 146 84 ns ns ns
Note
The hold time includes the time to hold the VOH and VOL under the load conditions of CL = 100 pF and
RL = 2 k. Remarks 1. The values in the above table are based on "fXX = 12 MHz and CL = 100 pF". 2. For a parameter with a dot (*) in the SYMBOL column, refer to "tCYX DEPENDENT BUS TIMING DEFINITION" as well.
44
PD78217A, 78218A
READ/WRITE OPERATION (2/2)
PARAMETER WAIT hold time from ASTB WAIT delay time from ASTB WAIT input time from RD WAIT hold time from RD WAIT delay time from RD Data input time from WAIT WR delay time from WAIT RD delay time from WAIT WAIT input time from WR (At refresh disabled) WAIT hold time Refresh disabled from WR WAIT delay Refresh enabled Refresh disabled
SYMBOL tHSTWT * tDSTWTH * tDRWTL * tHRWT * tDRWTH * tDWTID * tDWTW * tDWTR * tDWWTL * tHWWT1 * tHWWT2 * tDWWTH1 * tDWWTH2 * tDRRFQ * tDWRFQ * tWRFQL * tDRFQST *
TEST CONDITIONS No. of external waits = 1 No. of external waits = 1
MIN. 174
MAX.
UNIT ns
273 22
ns ns ns
No. of external waits = 1 No. of external waits = 1
87 186 62 154 72 22
ns ns ns ns ns ns ns
No. of external waits = 1 No. of external waits = 1 No. of external waits = 1 No. of external waits = 1
87 5 186 104 154 72 120 280
ns ns ns ns ns ns
time from WR Refresh enabled REFRQ delay time from RD REFRQ delay time from WR REFRQ low-level width ASTB delay time from REFRQ
Remarks 1. 2.
The values in the above table are based on "fXX = 12 MHz and CL = 100 pF". For a parameter with a dot (*) in the SYMBOL column, refer to "tCYX DEPENDENT BUS TIMING DEFINITION" as well.
45
PD78217A, 78218A
SERIAL OPERATION
PARAMETER
SYMBOL Input
TEST CONDITIONS External clock Internal divided by 16 Output Internal divided by 64 Input External clock Internal divided by 16 Output Internal divided by 64 Input External clock Internal divided by 16 Internal divided by 64
MIN. 1.0 1.3 5.3 420 556 2.5 420 556 2.5 150 400
MAX.
UNIT
s s s
ns ns
Serial clock cycle time
tCYSK
Serial clock low-level width
tWSKL
s
ns ns
Serial clock high-level width
tWSKH
Output
s
ns ns 300 ns
SI, SB0 setup time (to SCK) SI, SB0 hold time (from SCK)
tSSSK tHSSK tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) Open-drain output (SBI mode), tDSBSK2 RL = 1 k
0
SO/SB0 output delay time (from SCK)
0 4 SBI mode 4 4 4
800
ns tCYX tCYX tCYX tCYX
SB0 high hold time (from SCK) SB0 low setup time (to SCK) SB0 low-level width SB0 high-level width
tHSBSK tSSBSK tWSBL tWSBH
Remark
The values in the above table are based on "fXX = 12 MHz and CL = 100 pF".
46
PD78217A, 78218A
OTHER OPERATIONS
PARAMETER NMI low-level width NMI high-level width INTP0 to INTP5 low-level width INTP0 to INTP5 high-level width RESET low-level width RESET high-level width SYMBOL tWNIL tWNIH tWITL tWITH tWRSL tWRSH TEST CONDITIONS MIN. 10 10 24 24 10 10 MAX. UNIT
s s
tCYX tCYX
s s
EXTERNAL CLOCK TIMING
PARAMETER X1 input low-level width X1 input high-level width X1 input rise time X1 input fall time X1 input clock cycle time SYMBOL tWXL tWXH tXR tXF tCYX TEST CONDITIONS MIN. 30 30 0 0 82 MAX. 130 130 30 30 250 UNIT ns ns ns ns ns
A/D CONVERTER CHRACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = AVSS = 0 V)
PARAMETER Resolution 4.0 V AVREF VDD TA = -10 to +70C Overall error
Note1
SYMBOL
TEST CONDITIONS
MIN. 8
TYP.
MAX.
UNIT bit
0.4
%
3.6 V AVREF VDD TA = -10 to +70C 4.0 V AVREF VDD
0.8 0.8 1/2
% % LSB tCYX
Quantization error 82 ns tCYX < 125 ns (The FR bit of ADM is to be "0") Conversion time tCONV 125 ns tCYX < 250 ns (The FR bit of ADM is to be "1") 82 ns tCYX < 125 ns (The FR bit of ADM is to be "0") Sampling time tSAMP 125 ns tCYX < 250 ns (The FR bit of ADM is to be "1") 360
240
tCYX
72
tCYX
48 -0.3 AVREF +0.3 1000 3.6 VDD 1.5 0.2 5.0 1.5
tCYX V
Analog input voltage Analog input impedance Reference voltage AVREF current
VIAN
RAN AVREF fXX = 12 MHz AIREF Note 2
M V mA mA
5
Notes 1. 2.
Quantization error is not included. Represented by the ratio to full-scale value. When ADM register's CS bit = 0, in STOP mode. 47
PD78217A, 78218A
tCYX DEPENDENT BUS TIMING DEFINITION (1/2)
PARAMETER X1 input clock cycle time Address setup time (to ASTB) RD delay time from address Address float time (from RD) Data input time from address Data input time from ASTB Data input time from RD RD delay time from ASTB Address active time from RD ASTB delay time from RD RD low-level width ASTB high-level width WR delay time from address Data output time from ASTB SYMBOL tCYX tSAST tDAR tFAR tDAID tDSTID tDRID tDSTR tDRA tDRST tWRL tWSTH tDAW tDSTOD tDSTW1 WR delay time from ASTB tDSTW2 2tCYX - 35 (Refreshing enabled) Data setup time (to WR) Data setup time (to WR) ASTB delay time from WR tSODWR tSODWF (Refreshing enabled) tDWST tWWL1 WR low-level width tWWL2 tCYX - 40 (3 + 2n) tCYX - 50 (Refreshing disabled) (2 + 2n) tCYX - 50 (Refreshing enabled) WAIT input time from address WAIT input time from ASTB tDAWT tDSTWT 3tCYX - 100 2tCYX - 80 MAX. MAX. 146 84 ns ns MIN. 114
Note
FORMULA
MIN./MAX. MIN.
12 MHz 82 52 129 11 228 181 100
Note
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCYX - 30 2tCYX - 35 tCYX/2 - 30 (4 + 2n) tCYX - 100 (3 + 2n) tCYX - 65 (2 + 2n) tCYX - 64 tCYX - 30 2tCYX - 40 2tCYX - 40 (2 + 2n) tCYX - 40 tCYX - 30 2tCYX - 35 tCYX + 60 tCYX - 30 (Refreshing disabled)
MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MIN. MAX. MIN.
Note
Note
52 124 124 124
Note
52 129 142 52
MIN.
129
Note
ns
(3 + 2n) tCYX - 100 tCYX - 60
MIN. MIN. MIN. MIN.
146
ns ns ns ns
22 42 196
Note
ns
Remark Note
"n" indicates the number of waits. When n = 0
48
PD78217A, 78218A
tCYX DEPENDENT BUS TIMING DEFINITION (2/2)
PARAMETER WAIT hold time from ASTB WAIT delay time from ASTB WAIT input time from RD WAIT hold time from RD WAIT delay time from RD Data input time from WAIT WR delay time from WAIT RD delay time from WAIT WAIT input time from WR (At refresh disabled) WAIT hold time Refresh disabled from WR WAIT delay Refresh enabled Refresh disabled SYMBOL tHSTWT tDSTWTH tDRWTL tHRWT tDRWTH tDWTID tDWTW tDWTR tDWWTL tHWWT1 tHWWT2 tDWWTH1 tDWWTH2 tDRRFQ tDWRFQ tWRFQL tDRFQST FORMULA 2XtCYX + 10 2(1 + X)tCYX - 55 tCYX - 60 (2X - 1)tCYX + 5 (2X + 1)tCYX - 60 tCYX - 20 2tCYX - 10 tCYX - 10 tCYX - 60 (2X - 1)tCYX + 5 2(X - 1)tCYX + 5 (2X + 1)tCYX - 60 2XtCYX - 60 2tCYX - 10 tCYX - 10 2tCYX - 44 4tCYX - 48 MIN./MAX. MIN. MAX. MAX. MIN. MAX. MAX. MIN. MIN. MAX. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. 12 MHz 174 273
Note Note
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
22 87 186
Note Note
62 154 72 22 87 5
Note Note Note Note
186 104
time from WR Refresh enabled REFRQ delay time from RD REFRQ delay time from WR REFRQ low-level width ASTB delay time from REFRQ
154 72 120 280
Remarks 1. 2. 3. Note
X: The number of the external waits (1, 2, ...) tCYX 82 ns (fXX = 12 MHz) "n" indicates the number of waits.
When X = 1
49
PD78217A, 78218A
DATA RETENTION CHARACTERISTICS (TA= -40 to +85 C)
PARAMETER Data retention voltage Data retention current VDD rise time VDD fall time VDD hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage
SYMBOL VDDDR IDDDR
TEST CONDITIONS STOP mode VDDDR = 2.5 V VDDDR = 5 V 10 %
MIN. 2.5
TYP.
MAX. 5.5
UNIT V
2 5 200 200
20 50
A A s s
ms
tRVD tFVD tHVD
0
tDREL
0 Crystal resonator 30 5 0 0.9 VDDDR 0.1 VDDDR VDDDR
ms ms ms V V
tWAIT Ceramic resonator VIL VIH Specified pin
Note
Note
RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/INTP5, P27/SI, P32/SCK, P33/SO/SB0 and EA pins.
AC Timing Test Point
V DD-1 V 0.8 V DD or 2.2 V Test Points 0.8 V 0.45 V 0.8 V 0.8 V DD or 2.2 V
50
PD78217A, 78218A
Timing Waveform Read operation
tCYX X1
A8-A15 P60-P63 tDAR AD0-AD7 tSAST tHSTA tFAR tDSTID ASTB tWSTH tDSTR tDRID tWRL RD tDRST tHRID tDRA tDAID tHRA
Write operation
tCYX X1
A8-A15 P60-P63 tDAW AD0-AD7 tSAST tHSTA tDSTOD ASTB tWSTH tWWL1 tWWL2 WR tDSTW1 tDSTW2 tDWST tDWOD tSODWF tSODWR tHWOD tHWA
51
PD78217A, 78218A
External WAIT Signal Input Timing Read operation
A8-A15 P60-P63
AD0-AD7
tDWTID ASTB tDSTWTH tHSTWT tDRWTH tHRWT tDSTWT tDAWT WAIT tDRWTL tDWTR
RD
Write operation
A8-A15 P60-P63
AD0-AD7 tDWWTH1 tHWWT1 tDSTWTH tHSTWT tDWWTH2 tHWWT2 tDAWT WAIT tDWWTL tDSTWT tDWTW
ASTB
WR
52
PD78217A, 78218A
Refresh Timing Waveform Refresh after read
ASTB
RD tDRRFQ tDRFQST
REFRQ tWRFQL
Refresh after write
ASTB
WR tDWRFQ tDRFQST
REFRQ tWRFQL
53
PD78217A, 78218A
Serial Operation 3-wire serial I/O mode
tWSKL tWSKH
SCK tCYSK SI tDSBSK1 SO Output Data tSSSK tHSSK
Input Data
SBI Mode Bus release signal transfer
SCK tHSBSK SB0 tWSBL tWSBH tSSBSK
Command signal transfer
tWSKL tWSKH
SCK tHSBSK SB0 tSSBSK tCYSK tDSBSK2 tSSSK tHSSK I/O Data
54
PD78217A, 78218A
Interrupt Input Timing
tWNIH 0.8 VDD 0.8 V tWNIL
NMI
tWITH 0.8 VDD 0.8 V
tWITL
INTP0-INTP5
Reset Input Timing
tWRSH 0.8 VDD 0.8 V
tWRSL
RESET
55
PD78217A, 78218A
External Clock Timing
tWXH 0.8 VDD 0.8 V
X1
tXR
tXF tWXL
tCYX
Data Retention Characteristics
STOP Mode Setting
VDD tHVD tFVD
VDDDR tDREL tWAIT tRVD
RESET
0.8 VDD
0.8 V
NMI (Release by Falling Edge)
0.8 VDD
0.8 V
0.8 VDD NMI (Release by Rising Edge) 0.8 V
56
PD78217A, 78218A
7. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
Remark
ES versions have the same package drawings and use the same materials as mass-produced versions.
57
PD78217A, 78218A
64 PIN PLASTIC QFP (
14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark
ES versions have the same package drawings and use the same materials as mass-produced versions.
58
M
55
Q
PD78217A, 78218A
8. RECOMMENDED SOLDERING CONDITIONS
The PD78217A/78218A should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 8-1 Surface Mounting Type Soldering Conditions
5
PD78217AGC-AB8/78218AGC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm)
Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235 C, Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 2 times (1) After the first reflow process, cool the package down to room temperature , then start the second reflow process. (2) After the first reflow process, do not use water to remove residual flux. VPS Package peak temperature: 215 C, Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 2 times (1) After the first reflow process, cool the package down to room temperature , then start the second reflow process. (2) After the first reflow process, do not use water to remove residual flux. Pin temperature: 300 C or below, Heat time: 3 seconds or less (per each side of the device) VP15-00-2 Symbol IR35-00-2
Partial heating
---
Caution
Apply only one kind of soldering method to a device, except for partial heating method.
Table 8-2 Insertion Type Soldering Conditions
PD78217ACW/78218ACW-xxx : 64-pin plastic shrink DIP (750 mil)
Soldering Method Wave soldering (pin only) Partial heating
Soldering Conditions Solder temperature: 260 C or below, Flow time: 10 seconds or less Pin temperature: 300 C or below, Heat time: 3 seconds or less (per pin)
Caution
The wave soldering process must be applied only to pins, and make sure that the package body does not get jet soldered.
59
PD78217A, 78218A
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78217A/78218A. Language Processing Software
RA78K/II Notes1, 2, 3 CC78K/II Notes1, 2, 3 CC78K/II-L Notes1, 2, 3
78K/II series common assembler package 78K/II series common C compiler package 78K/II series common C compiler library source file
PROM Writing Tools
PG-1500 PA-78P214CW PA-78P214GC PG-1500 controller Notes1, 2 PROM programmer Programmer adapters connected to PG-1500
PG-1500 control program
Debugging Tools
IE-78240-R-A IE-78240-R Note4 IE-78200-R-BK IE-78240-R-EM IE-78200-R-EM Note4 EP-78210CW Note4 EP-78240CW-R EP-78210GC Note4 EP-78240GC-R EV-9200GC-64 SD78K/II Notes1, 2 DF78210 Notes1, 2
PD78218A subseries common in-circuit emulators
78K/II series common break board
PD78218A subseries evaluation emulation boards PD78218A subseries common emulation probes
Socket to be mounted on a user system board made for 64-pin plastic QFP IE-78240-R-A screen debugger
PD78218A subseries device file
Fuzzy Inference Development Support System
FE9000 Note1, FE9200 Note5 FT9080 Note1, FT9085 Note2 FI78K/II Notes1, 2 FD78K/II Notes1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
60
PD78217A, 78218A
Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM (PC DOSTM) based 3. HP9000 series 300TM (HP-UXTM) based, SPARCstationTM (Sun OSTM) based, EWS-4800 series (EWS-UX/ V) based 4. No longer manufactured and not available for purchase 5. IBM PC/AT (PC DOS + WindowsTM) based
Remark
For third-party development tools, see the 78K/II Series Development Tool Selection Guide (EF-231).
61
PD78217A, 78218A
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name Document No. (Japanese) IEU-755 IEU-754 IEA-607 IEA-700 IEA-686 IF-304 IEM-5101 IEM-5102 IEM-5532 Document No. (English) IEU-1313 IEU-1311 IEA-1220 IEA-1282 IEA-1273 IF-1160
PD78218A Subseries User's Manual: Hardware
78K/II Series User's Manual: Instruction 78K/II Series Application Note Fundamentals Application Floating Point Operation Program 78K/II Series Selection Guide 78K/II Series Instruction Table 78K/II Series Instruction Set
PD78218A Series Special Function Register Table
Development Tool Related Documents (User`s Manuals)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller IE-78240-R-A In-Circuit Emulator IE-78240-R In-Circuit Emulator Hardware Software SD78K/II Screen Debugger MS-DOS Based Introduction Reference SD78K/II Screen Debugger PC DOS Based Introduction Reference 78K/II Series Development Tool Selection Guide EEU-956 EF-231 EEU-1447 Document No. (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-777 EEU-651 EEU-704 EEU-796 EEU-705 EEU-706 EEU-841 EEU-813 EEU-1335 EEU-1291 EEU-1395 EEU-1322 EEU-1331 Document No. (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284
Caution
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
62
PD78217A, 78218A
Embedded Software Related Documents (User's Manuals)
Document Name RX78K/II Real-Time OS Basic Installation Debugger Technical Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System 78K/II Series Fuzzy Inference Development Support System 78K/II Series Fuzzy Inference Debugger Translator
Document No. (Japanese) EEU-910 EEU-884 EEU-895 EEU-885 EEU-829 EEU-862
Document No. (English)
EEU-1438 EEU-1444
Fuzzy Inference Module
EEU-860
EEU-1440
EEU-917
EEU-1459
Other Related Documents
Document Name QTOP Microcomputer Pamphlet Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer-Related Products Guide - Third Party Products Document No. (Japanese) IB-5040 IEI-635 IEI-616 IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604 MEI-1202 IEI-1213 IEI-1207 IEI-1209 Document No. (English)
Caution
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
63
PD78217A, 78218A
[MEMO]
64
PD78217A, 78218A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
65
PD78217A, 78218A
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78217ACW, 78217AGC-AB8 The customer must judge the need for license: PD78218ACW-xxx, 78218AGC-xxx-AB8
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11
MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. SPARCstation is a trademark of SPARC International, Inc. Sun OS is a trademark of Sun Microsystems, Inc. HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard Company.

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